The present invention relates generally to the bias control circuitry of multi-mode power amplifiers. More specifically, the present invention relates to a bias control technique that significantly improves the efficiency of a low-power mode in a multi-mode power amplifier.
Many wireless communication devices use Radio Frequency (RF) power amplifiers to ensure that RF signals attain sufficient strength to reach a base station. Since a power amplifier is one of the major power consuming components inside a wireless communication device, it is important to minimize its power consumption, and therefore, maximize battery time. A power amplifier usually transmits at various power levels, depending on the distance between the wireless communication device and the base station. The lesser the distance, the less power is required.
A typical power amplifier comprises a few bias circuits, one or two driver stages, an output stage, and a few matching circuits. The bias circuit determines the bias current for each amplifying stage. The driving stages ensure that the power amplifier achieves adequate amplification to achieve sufficient signal strength. The output stage generates the required power; and the impedance-matching circuits are used at the input and output of the power amplifier, to match input and output impedances.
In the operation of a linear power amplifier, sufficient bias current is required to achieve linearity at a given output power level. A linear power amplifier, designed for high-power operation, needs a relatively higher bias current than a linear power amplifier that is designed for medium- or low-power operation. As a result, a high-power linear power amplifier with a fixed bias current is inefficient when it is used at the medium- or low-power level. In general, the power-probability density function of a CDMA power amplifier peaks around 0 dBm during urban as well as suburban operations, i.e., most of the time, the CDMA power amplifier transmits close to 0 dBm power. A CDMA power amplifier, designed for high-power operation with a fixed bias current, will be inefficient at 0 dBm.
Various power amplifiers, which provide high and low quiescent currents for different output power levels, have been developed for high-frequency operations. One such power amplifier is described in US Patent Application Number 20040000954A1, titled ‘Power Amplifier Having a Bias Current Control Circuit’, assigned to Kim, Ji Hoon, et al. The bias circuit elaborated in this patent is capable of adjusting itself continuously, depending on the output power level. Since the power amplifier has two amplifying stages connected in the form of a cascade, both amplifying stages have to be enabled during high- and low-power operations. As a result, this configuration puts a low limit on bias current adjustment.
Another power amplifier is described in US Patent Application Number 20040056711A1, titled ‘Efficient Power Control of a Power Amplifier by Periphery Switching’, assigned to TriQuint Semiconductor, Inc. This power amplifier divides the output amplifying stage into two sections, with each section having its own separate bias circuit. Both output sections are enabled during high-power operation, whereas only one output section is enabled for low-power operation. Less bias current is required during the low-power mode; therefore efficiency at this mode is improved. The first amplifying stage and the second amplifying stage are always in a cascade configuration in high- and low-power operations. Further, the bias current is reduced only at the output stage and there is no bias current reduction in the first amplifying stage.
Yet another power amplifier is described in US Patent Application Number 20030016082A1, titled ‘High Frequency Power Amplifier Circuit Device’, assigned to Matsunaga, Yoshikuni et al. This power amplifier provides bias current control at each amplifying stage. Since all the amplifying stages are in a cascade configuration, it is not possible to disable the bias of any individual stage. As a result, the reduction in bias current is limited.
Another bias control circuit is described in U.S. Pat. No. 6,744,321, titled ‘Bias Control Circuit for Power Amplifier’, assigned to Information and Communications University Educational Foundation Republic of Korea. This bias circuit provides a two-level bias current control for a power amplifier, i.e., a high bias current for the high-power mode and a low bias current for the low-power mode.
In light of the above-mentioned facts, it is desirable to have power amplifiers with multiple bias current levels for different output power levels. Further, in order to enhance overall efficiency, it is desirable to have an optimized low bias current for power amplifiers operating at very low power levels such as 0 dBm or less.